1. Loop right offset ROR/RORD
1. Loop right offset ROR/RORD
1.1. Instruction Description
The instruction will cycle the input word (S) value to the right by N bits and load the result into the output word (D). If the number of shifts (N) is greater than or equal to 16 (RORD is 32), a modulo operation of modulus 16 (RORD is 32) will be performed before performing the cyclic shift, resulting in an effective number of shifts (N), so that the number of shifts is between 0 and 15 (RORD is between 0 and 31). If the number of shifts is greater than 0, the cyclic shift instruction is executed, and the last shifted value is copied to the shift instruction overflow flag (M8166). If the number of shifts is 0, the cyclic shift instruction is not executed, and the shift instruction zero flag (M8167) is set to 0.
When using signed data types, the sign bits are also shifted.
| Related registers | Description |
|---|---|
| M8166 | The last bit to be removed. |
| M8167 | The result of the shift operation is 0. |
1.2. The valid operands of the instruction
1.2.1. Single word Instruction(ROR)
| Input/Output | Data Type | operand | Description |
|---|---|---|---|
| IN1 | 16 bit unsigned integer | D/CV/TV/AI/AO/K/H/V/Z/FD, bit composite word (X/Y/M/C/T/S), local variable (LW) | Input |
| IN2 | 16 bit unsigned integer | D/CV/TV/AI/AO/K/H/V/Z/FD, bit composite word (X/Y/M/C/T/S), local variable (LW) | shift |
| OUT | 16 bit integer | D/CV/TV/AO/V/Z, bit composite word (Y/M/C/T/S), local variable (LW) | output |
1.2.2. Double word instruction(RORD)
| Input/Output | Data Type | operand | Description |
|---|---|---|---|
| IN1 | 32-bit unsigned integer | D/CV/K/H/FD, bit composite word (X/Y/M/C/T/S), local variable (LD) | input |
| IN2 | 32-bit unsigned integer | D/CV/K/H/FD, bit composite word (X/Y/M/C/T/S), local variable (LD) | shift |
| OUT | 32-bit integer | D/CV, bit composite word (Y/M/C/T/S), local variable (LD) | output |
1.3. Example
Command table
NETWORK 000
LD X000
ROR D0 K1 D1 // Shift D0 cycle by 1 bit to the right and output to D1
NETWORK 001
LD X001
RORD D2 K16 D4 // Cycle (D2, D3) to the right by 16 bits and output it to (D4, D5). In reality, D4=D3, D5=D2.
图1 ROR